1. Field of the Invention
This invention relates to a semiconductor integrated circuit, more particularly to the construction of a semiconductor integrated circuit comprising a plurality of bipolar CMOS (Bi-CMOS) gate arrays.
2. Description of the Prior Art
All memory cores in a conventional ROM formed by using bipolar CMOS gate arrays are made up of MOS transistors.
FIG. 1 is part of circuit diagram of a ROM which is made up of the conventional Bi-CMOS gate array. In the same diagram, each of a plurality of memory cells 4 is connected to a word line 5 and an output line i (a bit line 1). The source terminal 4S of the memory cell 4 is connected to a power source V.sub.DD (not shown) or a ground for programming. The drain terminal 4D of the memory cell 4 is connected to the output line 1.
When the memory cell 4 is addressed by a Bi-CMOS decoder 3 through a word line 5, data stored therein are read out on the output line 1. The memory cells 4 corresponding one word for word processing are connected to the output line 1.
In the conventional ROM having the construction described above, a Bi-CMOS are used as the decoder 3 or the sense amplifier 2 for high speed operation.
Moreover, because all of the drains of memory cells corresponding to the word for word processing are connected to the output line 1, the loads of the output line 1 becomes so heavy that there is a problem in the prior art that it takes much time to execute a reading operation the memory cells 4. Namely, the operation speed in reading become lower.
FIG. 2 shows reading forms for access time for the reading operation of the conventional ROM comprising the Bi-CMOS gate arrays. The number of the memory cells connected to the output line 1 is the same number of the memory cells corresponding to one word for word processing, as shown in FIG. 1.
In the same diagram, when an output level L.sub.o of the output line 1 exceeds a threshold level Ls of the sense amplifier 2, a reading operation of the data stored in the ROM is started (T0). The total access time of the reading operation for the ROM is given as follows: EQU T.sub.CMOS =T.sub.E -Ts
where the end time of the reading operation is T.sub.E and the time that an address signal is given to the Bi-CMOS decoder 3 is Ts.
In the ROM having the construction described above, as the memory cells belonging to the word line are connected to the output line 1 as loads, there is the problem that the rise-time (Ts-T.sub.o) of the reading operation of the memory cell 4 requires too much time.
FIG. 3 shows a basic cell as a unit cell of the Bi-CMOS gate array. In the same diagram, reference characters N1 to N4 designate N-type MOS transistors, P1 to P4 are P-type MOS transistors, NPN is a bipolar transistor, and R is a resistance. The Bi-CMOS gate array widely used is made up of a plurality of the basic cells arranged on a large-scale integrated (LSI) device, which are connected to one another by wiring. However, the bipolar transistor in the basic cell is not used in the conventional ROM so that the utilizable efficiency of the basic cell is lowered.
To summarize the problem of the conventional ROM implementing the Bi-CMOS gate arrays, a plurality of memory cells are connected to one output line so that the access time of the memory cell in the ROM is slowed and the degree of integration of the ROM becomes low because the Bi-transistor NPN in the basic cell has not been used.